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FPGA Design Elements
Charles Eric LaForest, PhD.
GateForge Consulting, Ltd.
This is a continually evolving document. Please email any feedback to
eric@fpgacpu.ca or Twitter @elaforest or join the Discord server.
Introduction
* Outline
* Licence and Disclaimer
References
* Verilog Coding Standard
* System Design Standard
* Rules for Ready/Valid Handshakes
* Useful Links
* References and Reading List
Tools
* v2h.py, which converts commented Verilog files into HTML files. Line
comments (no block comments!) are processed as Markdown. Thus, the web page
doesn't get stale as the code evolves. You will need the CSS Style file to
render everything the same, but it's in the repository and quite simple.
* verilinter, which is a small script using Verilator and Icarus Verilog to
lint Verilog-2001 files. This little tool catches a lot of simple and not
so simple Verilog mistakes and corner cases.
* generate_file_skeleton.py, which outputs a skeleton Verilog file in the
style used in this book. Takes no arguments. Simply pipe the output to a
new file or your text editor window.
* generate_instance.py, which generates a quick-and-dirty module instance
when given a filename containing a module definition as a parameter. When
code is highly modular, writing module instances takes a large fraction of
your writing time. This automates most of the grunt work. Pipe the output
to your text editor window. This is a quick hack made to work only with the
modules in this book.
* generate_fusesoc_core_file, which generates a local core file for FuseSoC,
the award-winning package manager and set of build tools for HDL code. This
allows you to integrate the FPGA Design Elements into your FuseSoC
projects.
* Intel Quartus Prime. The CAD tool suite for Intel (ex-Altera) FPGAs. It's
smaller and easier to run than Xilinx Vivado, and produces excellent
RTL-level and post-synthesis diagrams, which are very useful for checking
and debugging designs.
Useful Functions
* Max function
* Ceiling of log[2](N) function
* Word Count function
* Word Pad function
* Adjust to Multiple function
Simulation and Test Bench
* Synthesis Harness Input
* Synthesis Harness Output
* Simulation Clock
Boolean Logic
* Constant
* Bit Reducer
* Annuller
* Word Reverser
* Word Reducer
* Bit Shifter
* Number of Trailing Zeros (ntz)
* Number of Leading Zeros (nlz)
* Population Count
* Hamming Distance
* Bit Voting
* Multiplexer (Binary, Behavioural)
* Multiplexer (Binary, Structural)
* Multiplexer (One-Hot)
* Multiplexer (Bitwise, 2:1)
* Demultiplexer (Binary)
* Demultiplexer (One-Hot)
* Address Decoder (Static)
* Address Decoder (Behavioural)
* Address Decoder (Arithmetic)
* Address Translator (Static)
* Address Translator (Arithmetic)
* Extended Boolean operations
+ Bitmask 0 Bit at Rightmost 1 Bit
+ Bitmask 1 Bit at Rightmost 0 Bit
+ Bitmask Isolate Rightmost 1 Bit
+ Bitmask Next with Constant Popcount (via Population Count)
+ Bitmask Next with Constant Popcount (via Number of Trailing Zeros)
+ Bitmask Thermometer from Count
+ Bitmask Thermometer to Rightmost 0 Bit
+ Bitmask Thermometer to Rightmost 1 Bit
+ Bitmask Turn Off Trailing 1 Bits
+ Bitmask Turn On Trailing 0 Bits
+ Turn Off Rightmost 1 Bit
+ Turn Off Rightmost Contiguous 1 Bits
+ Turn Off Trailing 1 Bits
+ Turn On Rightmost 0 Bit
+ Turn On Trailing 0 Bits
* Dyadic Boolean Operator
+ Dyadic Boolean Operations
* Triadic Boolean Operator (Dual Output)
Synchronous Logic
* Register
* Register (with toggle input)
* Register (with asynchronous reset)
* Register Pipeline
* Simple Register Pipeline
* Memory
+ Single-Port RAM (one read/write port)
+ Simple Dual-Port RAM (one read port, one write port)
+ Simple Dual-Port RAM (one read port, one write port), with separate
read/write clocks
+ True Dual-Port RAM (two read/write ports)
+ Empty Memory Initialization File Generator
+ Multi-Ported Memory using Logic Elements, with Conflict Handling
+ Multi-Ported Memory using Replication (1WnR)
+ Multi-Ported Memory (LVT)
+ Multi-Ported Memory (XOR)
+ Multi-Ported Memory (I-LVT)
+ CAM
* Serial to Parallel Converter
* Parallel to Serial Converter
* Duty Cycle Generator
* Word Change Detector
* Bressenham Rate Converter
* Time Delay (cycles)
* Time Delay (fractions of seconds)
* Wall Clock
* Frequency Counter
Integer Arithmetic
* Width Adjuster
* Adder/Subtractor (Binary)
* Multiprecision Adder/Subtractor (Binary)
* Adder/Subtractor (Binary, Saturating)
* Adder/Subtractor (BCD)
* Carry-In (Binary)
* Arithmetic Predicates (Binary)
* Up/Down Counters
+ Binary
+ BCD
+ Grey
+ One-Hot
+ Johnson
* Number Encoding Converters
+ Binary to One-Hot
+ One-Hot to Binary
+ Binary to Gray (Reflected)
+ Gray to Binary (Reflected)
+ Binary to Johnson
+ Johnson to Binary
+ General Shift-Add Converter (e.g. Binary to multi-digit BCD, or to H/M/
S)
* Logarithm of Powers of Two
* Floor of Logarithm Base 2
* Ceiling of Logarithm Base 2
* Floor of Logarithm Base 10
* Multiplier (Binary, parallel)
* Multiplier (BCD, parallel)
* Multiplier (Binary, iterative)
* Multiplier (BCD, iterative)
* Divider (Powers of Two)
* Signed Integer Divider (Binary, iterative)
+ Signed Integer Remainder (Binary, iterative)
+ Signed Integer Quotient (Binary, iterative)
* Divider (BCD, iterative)
* Comparator
* Scaler
* Accumulator (Binary)
* Accumulator (Binary, Saturating)
* Accumulator (Min)
* Accumulator (Max)
* Accumulator (Mean)
* Accumulator (Weighted Mean)
* Averager (Powers of Two)
* Zero-Crossing Detector
* Pseudo-Random Number Generators (PRNGs)
+ Linear Feedback (Fibonacci) (self-synchronizing?)
+ PCG family
* Linear interpolation from table (2^n size)
Pulse Logic
* Pulse Latch
* Pulse Generator
* Pipeline to Pulse Interface
* Pulse to Pipeline Interface
* Pulse Divider
Elastic Pipelines
* Pipeline Skid Buffer
* Pipeline Half-Buffer
* Pipeline FIFO Buffer
* Skid Buffer Pipeline
* Pipeline Credit Buffer
* Pipeline Fork (Lazy)
* Pipeline Fork (Eager)
* Pipeline Join
* Pipeline Branch (One-Hot)
* Pipeline Merge (One-Hot)
* Pipeline Merge (Priority)
* Pipeline Merge (Round-Robin)
* Pipeline Sink
Arbitration and Synchronization
* Priority Encoder
* Priority Arbiter
* Round-Robin Arbiter
* Synchronous Muller C-Element
Clock Domain Crossing (CDC)
* A Primer on CDC Theory
* CDC Bit Synchronizer
* CDC Word Synchronizer
* CDC Pulse Synchronizer (4-phase)
* CDC Pulse Synchronizer (2-phase)
* Weinstein Flancter
* CDC Flag Bit
* Reset Synchronizer
* CDC FIFO Buffer
Interfaces
* I/O Register (Single-Ended)
* Debouncer (Low Latency)
* Quadrature Decoder
* Seven-segment Display Decoder (single BCD digit)
* Key Encoder (NxM, no rollover)
* Stepper Motor Driver
* Servo Motor Driver
* Basic I2C (just enough to read/write one address upon a trigger)
* Basic UART (no flow-control, no FIFO, fixed rate via parameter, enough to
receive simple commands, or dump data)
* Basic NeoPixel Driver (really another kind of UART)
Analog Signal Handling
* Basic waveform generator (table-driven)
* PWM driver (for sound, motor, LEDs)
* Sound sample player (simple DAC data, played as PWM?)
* Basic DAC (PMW and output to resistor ladder)
* Basic ADC (SAR using PWM DAC and LVDS input)
* Sound sample recorder (ADC + Memory)
Hashing and Pattern Matching
* Simple substring match
* Hash Functions (misc. TBD)
* Bloom or Cuckoo Filter
Communications
* Clock encoding and recovery (e.g. NRZ, MFM, DM, etc... as in old magnetic
storage)
* Basic LVDS/TMDS communication (like UART, building block for LCD control,
HDMI, multi-FPGA design, serial wire mux)
* Pseudo-differential communication (slower, using regular pins)
* Single-wire communication (tri-state bidir pin, self-clocked like NeoPixel)
* Hamming Code Generator
* Hamming Code Checker (EDAC)
* CRC Generator
* CRC Checker
* 8b/10b Encoder
* 8b/10b Decoder
Miscellaneous Bits
* On The Implementation of Finite State Machines
* Open Design Questions
* Using [S:Altera's:S] Intel's USB-Blaster on Debian Linux
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